This invention relates to a procedure and resources for identifying an operating mode of a device, called a controlled device, with which a communication is established according to a protocol that is designed to send, at specific times, a signal by the controlled device. This signal can be a return signal in response to a message received, to indicate that the message has been received according to the protocol. This type of signal does not necessarily indicate the mode in which the controlled device operates when sending this signal. When there are several different operating modes for the controlled device, it may be impossible to obtain the current one, particularly if the apparent behavior of the controlled device is the same for two or more possible modes. As an example, these modes can correspond to a normal operating mode and to one or several test modes of the controlled device. The modes can be controlled by internal or external signals of the latter. These signals can also be inside or outside the communication protocol.
For example, the controlled device can operate according to a normal mode and a set of test modes that are different from the normal mode, principally at the configuration level of certain signals, so that it is impossible or difficult to distinguish from the outside between a normal mode and a test mode, or between two different test modes.
This problem is found, among others, in peripheral devices or components that are controlled by a controller or equipment. For example, with semiconductor memories, such as programmable memories and electrically erasable memories (called EEPROM, Electrically Erasable and Programmable Read-Only Memory) that include at least one read and/or write test mode.
There are established communication protocols with memory, in particular, the protocol known by the acronym I2C bus/protocol (I2C stands for “inter integrated circuit”), an analog protocol that allows exchanging data with a memory. These protocols can be used to control a memory, for example, using a command device such as a microcontroller or a test tool. This case is represented by the block diagram in FIG. 1.
The problem then lies in verifying whether the memory has correctly recognized a command to go into test mode and whether it has not remained in normal mode for whatever reason.
Typically, the correct receipt of data is verified using an acknowledgement message, call ACK (acknowledgement) transmitted by the recipient. The bits of the data exchanged, including the ACK signal are transmitted to the clock frequency. In the I2C protocol, exchanges to or from the memory operate on a transmission bus using eight-bit strings, each followed by an ACK bit. The latter is expressed by taking the capacity of the transmission bus at 0. For example, in a dialogue over a bus 6 at the I2C protocol between a microcontroller (MC) 2 and a memory (M) 4 in write mode, an exchange can take on the following form:
MC: transmission of the command “device selection” (DS), encoded over eight bits, that indicates that it is a read or write operation. At the cycle of the ninth bit, the MC goes into standby mode to await a response by the memory.
M: response transmission of an ACK bit, by taking the capacity of the bus at 0 during the above-mentioned ninth cycle.
MC: having been informed of this bias of the taking into account (acknowledgement) of the command, transmission of the data to be written (for a write operation) on an eight-bit string.
M: transmission of an ACK bit indicating the acknowledgement the eight-bit string of data.
The acknowledgement can be in both directions. Therefore, in the above-mentioned example, the MC can also send an ACK bit to indicate to the memory the acknowledgement of a data element sent by the memory.
At the memory level, dialogue management is ensured by a logical part of the application, which can be in the form of a “programmable logic array” or “PLA” residing in the memory M.
The main elements of the memory are identified in the block diagram in FIG. 2, which includes:                a memory layer 8, comprising a data storage cell matrix,        an address decoder 10, which allows accessing the cells specified by the addresses provided,        a read circuit 12, which allows outputting, in an adapted manner, the data read by the memory layer, and        the application logic, here in the form of PLA 14, which manages the various operating modes by a state machine.        
The I2C bus operates over four main wires: a two-way data transmission wire SDA, a clock signal transmission wire SCL, and two Vcc and GND power supply wires. The following are added to the latter: a write-protection wire, WP (write protect), and memory selection wires (normally three wires called E0, E1, and E2). These three wires allow encoding 16 different memory addresses, for example, to cover 16 KB in units of 1 KB.
To select a specific memory, the first string of eight bits sent by the microcontroller (or any other element communicating with the memory) indicates the type of protocol over the first four bits; that is, the device type identifier, and on the next three bits E0, E1, and E3, the memory selected according to the expected encoding remains for this memory. The eighth bit indicates whether it is a read or write operation. The eight consecutive bits transmitted over the SDA line are named b7 (first bit transmitted), b6, . . . b0 (last bit) This sequence is summarized in Table 1.
TABLE 1Example of device selection encodingValidation (ChipDevice type identifierEnable)RWbarb7b6b5b4b3b2b1b01010E2E1E0RWbar
The start and end of a statement are signaled by the bias of a particular combination of logical states of the SCL and SDA signals, as indicated by the chronogram in FIGS. 3a, 3b, and 3c. These chronograms represent, respectively, a sequence on the totality between a start condition and a stop condition (FIG. 3a), the first nine bits exchanged at the beginning (3b) and the last nine bits exchanged before the stop (FIG. 3c).
For the start of the statement, the above-mentioned combination is a high-low transition over the SDA signal while the SCL signals are in the high state. All the memories on the bus are activated—in standby mode—at the time of the start operation. The selected memory is indicated by the fifth, sixth, and seventh bits (E0, E1, E2). At that time, all unselected memories are deselected automatically. The selected memory detects the eighth bit b0 (indicating a read or write operation) and, at the ninth cycle, returns the ACK signal. The microcontroller will then be informed that the selected memory has correctly taken the protocol into account. At this stage, the first memory selection string will have been acknowledged.
In the case of a data write operation, represented by the chronograms in FIGS. 4a and 4b, the microcontroller can either write a single byte (chronogram in FIG. 4a), or write a series of bytes to the consecutive addresses of the memory, which is designated by the page write term (chronogram in FIG. 4b). As indicated in FIGS. 4a and 4b, the microcontroller first transmits a string that includes the write address, then the data over a single eight-bit string (FIG. 4a) or over several strings (FIG. 4b); the number of strings varies from one to sixteen, allowing transmission of up to sixteen eight-bit words. Each string is followed by an ACK bit transmitted by the memory. After the ACK bit of the last string of the last word, the end of the statement is indicated by the combination of SDA and SCL signals constituted by the low-high transition of the SDA signal, with the SCL signal remaining in high state (FIG. 3).
The memory includes a write command pin, called WCbar, which allows denying the writing of data when in state 1. In particular, it allows programming data into the memory and then blocking against any future write operations by connecting the pin to the Vcc power supply. Note that in the chronograms in FIGS. 4a and 4b, the WCbar state is 0. Nevertheless, the memory can be selected and the address bytes can be acknowledged when WCbar is at 1.
The chronograms in FIGS. 5a, 5b, and 5d represent the case of a read operation of the memory according to various modes: reading at the current address (FIG. 5a), reading at a designated address (FIG. 5b), sequential reading from the current address (FIG. 5c), and sequential reading from a designated address (FIG. 5d).
In read mode, the read address designation in the memory operates using a false write operation (FIGS. 5b and 5d). Indeed, the I2C protocol does not foresee the specific address designation command in read mode, but only a write address. Thus, a read operation passes through the transmission of a memory selection through bits E0, E1, and E2, as explained above, then, to the next string, of the address (BYTE ADDR) that corresponds to the read operation location. Nevertheless, instead of following this operation by sending write data, the beginning condition is repeated by again selecting the memory. Only this time, the RWbar bit is placed, not at the low level, as in the write operation, but rather at the high level. This level indicates that the write operation is aborted and that it is indeed a read operation. In response, the memory produces the data of this address on the I2C bus. The ACK signal is then transmitted to each received byte. Note that in this case the ACK signal is transmitted after each consecutive byte by the target device of read data (the microcontroller in this case), and not by the memory.
When only one byte is to be read, the target device emits, when it receives it, a NO ACK signal (active in high state), interrupting the read process of the other data in the memory (FIG. 5a). Indeed, the PLA assumes that any read operation is sequential on consecutive addresses, unless otherwise indicated.
When a read operation of the memory is done from a current address, already designated by a pointer, the operation does not need the address (FIGS. 5a and 5c). This sample case can arise when a data element must be read immediately after it has been written into the memory.
The PLA can be considered as a state machine that manages all the memory operations on the periodicities of nine bits, each comprised of an eight-bit word and a ninth ACK bit. An internal counter is thus foreseen to count the clock cycles.
Before providing a memory to the client, typically an equipment manufacturer, the manufacturer normally performs a series of tests according to various modes. These modes generally use the same protocols as the client modes. In other words, for these tests, exactly the same protocol as the one presented to the client in the notices and specifications (see FIGS. 3, 4, and 5, for example) is used. To distinguish the test modes from the client mode, for the former high-voltage pulses (relative to Vcc) are used and applied to the control pin when writing the WCbar mentioned above. These pulses are applied at different times of the protocol: the arrival time of such a pulse indicates which of the test modes will be used.
Recall that there are three possible states of a memory cell, identified by voltage values VT through the floating grid transistor of the cell, as follows:                virgin: VT=approx.+1V        written (programmed): VT=approx.−1.5V        erased: VT=approx.+3V        
One of the test modes is a read test designed to determine whether the memory cells have suffered some loss of written or erased data. The reading of a memory cell is done by comparing the level of its voltage with an intermediary threshold voltage CGint produced internally.
This CGint threshold leaves a relatively significant margin with respect to the erase and write limit voltages, which allows accommodating for possible manufacturing derivations or aging. One of the tests performed, called CGext, consists in replacing the CGint threshold by an external threshold, CGext, which is closer to the value foreseen for the state of the cell to be detected that is not the CGint internal threshold.
Typically, the value of the CGext voltage is applied to the WCbar pin at a predetermined time during the read operation. The value of this CGext threshold is chosen in order to provide less tolerance to a possible decline in cell programming voltages to monitor the cells excluded from a project specification, but that could work correctly in client mode given the more tolerant CGint internal threshold.
In other words, in this test mode, a narrower correct operation margin than that of the client mode is imposed. As a result, a memory that lies outside the margins in test mode but within the margin in client mode will read output the data that indeed correspond to the write operation when in client mode, but would produce, on the other had, errors during the reading of the same data in test mode because of the increased severity of the recognition threshold.
To illustrate, FIG. 6 shows, on a vertical voltage scale that increases towards high positive values passing through the peak, the CGint, CGext relative positions for the case of the detection of a cell that is presumed to be at the programming stage, as well as the write (programming) voltage limits. The voltage for this cell must therefore be negative, approximately −1.5V. Typically, the CGint value is fixed close to 1V, for technological reasons. The CGext intermediary voltage is generally given the lowest possible positive value, normally approximately −0.5V (lower threshold values are not generally exploitable).
In order to be able to validate a memory on such a test, first it is necessary to ensure that the memory has recognized the CGext test mode command and that it has not remained untimely in client mode. Analogous considerations are applied for other tests, whether they are reading tests or writing tests.
Therefore, there is no return of memory information that allows verifying whether the command that was transmitted to it has been placed in test mode and acknowledged correctly. In the next steps, the voltage applied on the WCbar pin to establish a test mode will be designated as high voltage, because it is typically a high potential on the order of 12V.
Additional information on the I2C protocol is available from several sources, including the technical notice regarding the serial type of the 16/8/4/2/1 Kbit EEPROM family over the I2C bus of the requesting company, product reference: M24C16, M24C08, M24C04, M24C02, M24C01, publication dated July 02.